Computer graphics display systems, e.g. Graphics Workstations, are used to generate and display two dimensional and three dimensional images for the scientific and engineering community, film industry, and other disciplines. These graphics images are digitally represented and stored in a frame buffer that is comprised of a plurality of VDRAMS arranged in an array fashion. The rate at which the digital information stored in the frame buffer can be accessed is a critical parameter in the performance of the image rendering.
Most DRAMs store the digital information in a two dimensional array of cells arranged in rows and columns. Rows are referred to as Wordlines and columns as Bitlines. A cell can be uniquely addressed by selecting its associated Wordline and Bitline. The DRAM supports both a read and write operation to each cell (other operations are supported but are not relevant to the present invention). Both operations require a row address presented on the address input pins during a RAS (Row Address Strobe), and a column address presented on the address pins during a CAS (Column Address Strobe). The state of the WE (Write Enable) pin is evaluated to determine if a read or a write operation is to be performed. For a read operation, the row address is decoded to determine the wordline vector. The selected wordline cell's polarity is presented on a bitline which is connected to a primary sense amplifier that amplifies and latches the cell data. The column address is decoded and the associated bitline is presented to a data line, which transfers the data to a secondary sense amplifier, whose output is latched in a hold latch. The data is then processed to the OCD (Off Chip Driver), which presents data to tile output pins of the DRAM.
A write operation parallels the read operation until the column address decoding. At this point, new data is asserted on the Data In pins and write drivers transfer the new data to the data lines, over-writing the sense amplifiers and rewriting the new data into the cells.
A VDRAM is a derivative of the conventional DRAM with additional video features including a serial-out/parallel-in register connected to a Secondary Serial Port. This secondary port allows asynchronous scanout of the VDRAM data independent of the conventional DRAM primary data port read and write operation described above. The serial-out/parallel-in register, conventionally referred to as a SAM (Serial Access Memory), is connected to tile DRAM memory array such that a wordline S data can be read into the SAM in parallel fashion and data can be read from the SAM serially by initiating a clock cycle.
VDRAM scanout performance can be improved by increasing the Secondary Port access cycle time and by optimizing the associated circuitry. This method improves performance until the clock cycle period becomes shorter than the time required to fetch data from the Serial Register and present it to the Secondary Port data out pins. Under this condition valid data is not available since it fails to appear at the secondary port output pins before the next clock cycle.